FIG. 1 is a diagram showing the configuration of a conventional CML (Current Mode Logic) driver circuit. The CML driver circuit includes N channel MOS transistors (NMOS transistors) N1 and N2, composing a differential circuit and constituting a switching device. The NMOS transistors N1 and N2 have coupled sources connected to a constant current source CS, have gates connected to differential input terminals INT and INB, respectively and have drains connected to a power supply VDD via output resistors Rout1 and Rout2. The drains of the NMOS transistors N1 and N2 are also connected to differential output terminals DOT and DOB, respectively. The differential output terminals DOT and DOB are connected to both ends of termination resistors Rterm1 and Rterm2, with the output potential being of an analog level.
The CML driver circuit, shown in FIG. 1, is of a circuit configuration generally used in high-speed differential signal transmission. However, since a constant current source is needed, it is supposed that current consumption tends to be increased.
In particular, there is no marked difference in characteristics of SerDes macros (interface macros each including a serializer for parallel-serial converting parallel data and serially outputting the resulting data at an output buffer circuit and a deserializer receiving the serial data at an input buffer and serial-parallel converting the so received serial data), manufactured by competing vendors, as long as the SerDes Macros manufactured are those that meet relevant standards. It is noted that each of the SerDes macros of different vendors carries larger numbers of CML drivers thereon. As a matter of fact, it is the power consumption which mainly determines the dominance of products by the different vendors.
The waveform of a transmission signal tends to deteriorate due to the increase of transmission speed and the increase of transmission distance. With wide spread use of a broadband system and high speed transmission, waveform deterioration, ascribable to transmission line loss, as shown schematically in FIG. 2, is becoming of serious concern. In case the transmission side (output buffer circuit side) is not equipped with preemphasis function which emphasizes the amplitude of the output signal at the time points of output signal transitions, the amplitude at the transition point of the signal which has been transmitted on the transmission line and received by a receiving end, has get attenuated by distortion.
In particular, in the transmission of the GHz order, the logarithm of the signal attenuation, ascribable to the skin effect and dielectric loss, is increased in direct proportion to the logarithm of the frequency. For this reason, an output waveform is intentionally subjected to overshooting, on the transmission side, at the rise time of an output signal waveform, based on the preemphasis function, as shown in FIG. 3, to prevent waveform deterioration otherwise caused on the receiving side, that is, to prevent the jitter from increasing. This preemphasis function has proven indispensable means for transmission on the GHz order.
It is now assumed that, in FIG. 1, an input differential signal of the waveform shown in FIG. 4 is supplied to gates INT and INB of NMOS transistors N1 and N2. If, at a timing t3 of FIG. 4, a HIGH side potential and a low side potential are supplied to the gates INT and INB of the NMOS transistors N1 and N2, respectively, the NMOS transistors N1 and N2 are turned on and off, respectively. This establishes the following two current paths between the power supply potential VDD and the ground:
(1) A current path of output resistor Rout1→NMOS transistor N1; and
(2) another current path of output resistor Rout2→termination resistor Rterm1→termination resistor Rterm2→NMOS transistor N1.
In this case, the output terminal DOT is at a high potential, and the output terminal DOB is at a low potential. Meanwhile, in case the input logic is reversed, as indicated from a timing t5 to a timing t6 in FIG. 4, the output logic is such that the output terminal DOT is at the low side potential and the output terminal DOB is at the high side potential. The ratio between two currents is determined by the values of output resistors and termination resistors and, from these values of the currents and the resistances, the output potential and the amplitude (high side potential minus low side potential) are determined.
An amplitude Vout, an output high voltage VOH of the output signal and an output low voltage VOL of the output signal, at a timing t1 in FIG. 4, are indicated by the following equations (1), (2) and (3) respectively:Amplitude Vout=I×{Rout1/(Rout1+Rout2+Rterm1+Rterm2)}×(Rterm1+Rterm2)  (1)output high voltage VOH=VDD−{Rout2×I×{Rout1/(Rout1+Rout2+Rterm1+Rterm2)}}  (2)output low voltage VOL=VDD−{Rout1×I×{(Rout2+Rterm1+Rterm2)/(Rout1+Rout2+Rterm1+Rterm2)}}  (3)
In the above equations, the symbols used correspond to those of FIG. 1.